Conventionally, a build-up substrate having an insulating layer and a wiring layer layered on upper and lower surfaces of a core layer is used as a wiring substrate for a semiconductor package for mounting a semiconductor chip thereon.
In recent years, size-reduction of electronic devices mounted with semiconductor packages is progressing. Along with such progress, further size-reduction and high densification of wiring layers are being demanded for wiring substrates used for semiconductor packages.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2003-023252
However, there are limits to increasing the flatness of the surface of the wiring substrate and reducing the diameter of a via by laser processing. Further, forming the wirings into fine sizes is also limited. Thus, it is difficult to meet the demands for high densification of wiring layers.